FPGA LED blinking Example

Led blinking example is considered a hello world program for any Hardware based softwares. So today we are going to blink the LED in my Nexys 3 Board. This example will serve the both examples, VHDL as well as Verilog. First of all we will look for the VHDL example.

VHDL LED blinking Code

Here is the simple code for LED blinking. Because our board is using the 100MHz Clock so we need to divide that Clock to 0.5Hz. I created a simple clock counter and once this counter reaches 50,000,000 I toggle one bit and reset the counter. Later on this toggled bit is used to attach with the LED.

Here is the complete code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity blinky_ex01 is
    Port ( clk : in  STD_LOGIC;
           led : out  STD_LOGIC);
end blinky_ex01;

architecture Behavioral of blinky_ex01 is
 signal clk_counter : natural range 0 to 50000000 := 0;
 signal blinker : std_logic := '0';
begin
 
 process(clk)
 begin 
  if rising_edge(clk) then 
   clk_counter <= clk_counter + 1; 
   if clk_counter >= 50000000 then 
     blinker <= not blinker;
     clk_counter <= 0;
   end if; 
  end if; 
 end process;
 
 led <= blinker;
end Behavioral;
Code language: PHP (php)

and for the constraint file Only these two assignments are required. These could be found in reference manual of the board.

NET "led" LOC = U16;
NET "clk" LOC = V10;Code language: JavaScript (javascript)

Verilog LED Blinking Code

Now we are going to do the same in the verilog and you will notice how simple it is in verilog. So Let’s first look into the code.

module stepper_ex01(
    output LED,
    input clk    
    );
  
integer counter;
reg state;

always @ (posedge clk) begin
    counter <= counter + 1;
  if(counter >= 50000000 )begin
  counter <=0;
  state <= !state;
  end
    
end
  
assign LED = state;  

endmodule
Code language: JavaScript (javascript)

The constraint file will be used the same one which we used for the VHDL version.

Also keep in mind that there could be some other variations as well but the thing to remember is to do it in a process or always block. You need the system clock signal. This signal is feed to the FPGA on the board. You don’t have to do anything to the clk signal other then just finding the right attachment for your board. Also you need to find out the system frequency for your board as well. Rest is the similar for any board.